Seminars
Thu |
CMOS Photonics | |
Co-sponsored by the IEEE Electron Devices Society | ||
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Abstract: In the past decade, silicon has moved from a work bench for low-index contrast photonics to a strong-confinement (SC) photonics workhorse. Much of the interest in silicon photonics has been generated by the long term goal of integrating these new devices with high performance CMOS electronics. Benefits of this integration include leveraging the energy efficiency and bandwidth density of photonic interconnects to solve the communication bottleneck currently limiting microprocessor performance. To succeed, however, we believe silicon photonics must evolve from being fabricated on platforms that are incompatible with high density electronics to being manufactured in the existing high volume CMOS process flow. In this aim, we have developed an integration platform from CAD design to wafer-scale post-processing that allows for foundry-transparent fabrication of photonic devices in existing CMOS processes. This talk will present our integration platform and our initial results from electronic-photonic test chips fabricated as a multi-project wafer (MPW) customer in three different sub-100nm CMOS processes from two major semiconductor manufacturers. Biography: Jason S. Orcutt received his B.S. degree in Electrical Engineering from Columbia University in 2005. While there, he used commercial silicon VLSI fabrication technology to design experimental hybrid carbon nanotube circuits and biological interfaces with Professor Ken Shepard. Jason is currently a Ph.D. candidate in Professor Rajeev Ram’s laboratory in the Research Laboratory of Electronics at the Massachusetts Institute of Technology. His previous work with Professor Ram focused on the measurement and modeling of defected germanium on silicon photodiodes leading to an M.S. degree in 2008. His current work focuses on the direct integration of photonic devices with existing commercial scaled CMOS processes. Jason is the recipient of a National Science Foundation Graduate Research Fellowship. Location: MIT Lincoln Laboratory |
