Boston Chapter of the IEEE Photonics Society

Abstract:  Photonic integrated circuits (PICs) made using traditional CMOS-compatible materials (e.g., Si, SiO2, SiNx, Ge) and fabrication processes can have excellent integrated passive components while leveraging existing silicon processing infrastructure, but are often limited by the lack of on-chip optical gain, high-speed modulation, and photodetection. Meanwhile, III-V semiconductor materials (e.g., GaAs, InP, GaN) can make best-in-class optoelectronic devices such as lasers and photodetectors, but lag in passive performance and PIC scalability. To get the best of both worlds, III-V and Si-based photonic devices have traditionally been integrated into hybrid PICs by using flip-chip bonding or layer transfer approaches where small numbers of III-V devices are grown on native substrates and then serially placed within larger Si-based PICs. Unfortunately, these existing approaches do not scale well to large numbers of active devices or highly complex PICs.

Here we present an alternative approach, known as heteroepitaxial photonic integration, where III-V active components are grown directly in their final positions within the PIC, using the Si substrate as an epitaxial template. The key advantage of this approach is the fully parallel wafer-scale nature of the heteroepitaxial growth process, enabling vastly increased active component count, higher system complexity, and better mass-manufacturability of hybrid PICs. This could impact application areas such as trapped ion quantum computing and timekeeping, direct-diode beam combining for high-energy lasers, and chip-scale LIDAR. Risks of heteroepitaxial integration include adverse impact of crystalline defects on III-V device performance as well as optical coupling between Si-based passive and III-V active components. Progress towards mitigation of these risks will be discussed, including demonstration of efficient optical transitions between heteroepitaxial III-V and SiN waveguides.

Biography:  Dr. Christopher Heidelberger is a technical staff member in the Quantum Information and Integrated Nanosystems Group at MIT Lincoln Laboratory. His research interests include semiconductor epitaxy, microfabrication, and characterization for advanced microelectronic and optoelectronic devices. He leads the semiconductor epitaxy efforts for the Integrated Photonics Team, including heteroepitaxial integration of active III-V photonic devices with silicon-based photonic integrated circuits and growth of germanium/silicon heterostructures for mid-wave infrared photonic integrated circuits. He is involved with development of component-level optoelectronic devices, including slab-coupled optical waveguide lasers and waveguide photodetectors. He also collaborates with the Advanced Imager Group on development of next-generation Geiger-mode avalanche photodetector arrays.

Chris received a BS degree in materials science and engineering from Cornell University and a PhD degree in the same field from MIT. His doctoral work focused on organometallic vapor phase epitaxy of III-arsenide/phosphide films on silicon substrates for monolithic integration of III-V microelectronics with Si CMOS circuitry. He has coauthored more than 20 peer-reviewed publications and two patents. He was a recipient of the IBM PhD Fellowship and was selected as a DARPA Riser in 2022.

Location:  MIT Lincoln Laboratory Forbes Road